// ------------------------------------------------------------------------------
// FileNmae : converter.v
// Function : Converts a register value to the same value assigned to the 
//            lower-order bits in a bus of configurable width.
//
// ------------------------------------------------------------------------------
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-06-28
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
// -----------------------------------------------------------------------------

//module converter #(parameter WIDTH = 4, PAD_NUM = 0) // parameter defaults.
module converter #(parameter WIDTH = 4, PAD_NUM = 1) // parameter defaults.
       (output[WIDTH-1+PAD_NUM:0] out_bus,  // default variable type: wire 
        input [WIDTH-1:0]         in_bus,   // header port IEEE1364-2001 
        input                     enable
       );
  
  reg[WIDTH-1+PAD_NUM:0] bus_reg;      // internal variables; Retains current count value.
  reg[WIDTH-1+PAD_NUM:0] out_bus_gate; // Retains three-state.
  
  // --------------main code --------------------------------------------------------
  // Keep bus_reg always updated (combinational circuit): assign, always@(level_list)
  always@(in_bus) // list sensitivity
  begin
    // This could be done by concatenation, a later topic:
    // bus_reg[WIDTH-1:0] = in_bus;
    if (PAD_NUM!=1'b0) begin
      bus_reg[(WIDTH-1+PAD_NUM):WIDTH] = 'b0; // PAD with 0.
      bus_reg[WIDTH-1:0] = in_bus;
    end
    else // syn-RTL coding style, if not => latch
      bus_reg[WIDTH-1:0] = in_bus;

  end
  
  // Next block controls the state of the output drivers:
  always@(enable, bus_reg) // IEEE-1364 1995 "," => "or'
  begin
    if (enable==1'b1)
         #2 out_bus_gate = bus_reg;
    else #1 out_bus_gate = 'bz; // Set high-impedance.
  end
 
  // assign out_bus_gate = enable ? bus_reg : 'bz;

  // Connect output drivers to output pins:
  assign out_bus = out_bus_gate;

endmodule// converter

